1. Field of the Invention
Embodiments of the present invention relate to mixer circuits for use in communication systems, and in preferred embodiments, to an apparatus and method for tracking a DC offset in a direct conversion passive mixer circuit used in wireless communication systems and for providing local oscillator DC bias level-shifting to reduce even order distortion, including second order intermodulation (IM2) distortion, resulting from the DC offset, and to wireless communication systems that employ such an apparatus and method.
2. Description of Related Art
Mixers are used in transceivers in many commercial wireless applications, including wireless Local Area Networks (LANs), wireless personal communication devices including radios, cellular telephones, mobile cordless telephones, Personal Digital Assistants (PDAs), Personal Computer Memory Card International Association (PCMCIA) computer interface applications, telemetry systems, global positioning systems (GPS) and other radio frequency (RF) devices.
In such applications, the transmitted and received signal is an RF signal. The RF signal consists of a baseband signal modulated on a carrier frequency signal. Because the baseband signal is a relatively low frequency signal, the baseband signal is modulated onto the higher frequency carrier signal before transmission. Conversely, because the carrier frequency is a relatively high frequency signal, the RF signal is down-converted to a lower frequency upon reception and before further processing.
Conventional heterodyne receivers down convert a RF signal to a baseband signal using one or more intermediate stages in which the RF signal is converted to one or more intermediate-frequency signals, lower than the RF signal, until the base-band frequency is reached. A heterodyne transmitter generates a higher frequency RF signal from a baseband signal using one or more intermediate stages to up-convert the frequency.
A homodyne or “direct conversion” receiver directly down-converts RF signals to baseband frequency without intermediate stages. Analogously, a direct conversion transmitter up-converts from base-band to RF without intermediate stages. A direct conversion receiver may be defined more generally as a receiver that directly converts any frequency to DC. Direct conversion transceivers are particularly useful in multi-band transceivers, because of the elimination of the intermediate frequency passband filtering components and the resulting space savings. In addition, in direct conversion transceivers there is a corresponding reduction in the complexity of the transceivers.
Mixers are used in transceivers to convert a signal from a low frequency to a high frequency or a high frequency to a low frequency by mixing the signal with a local oscillator signal. The local oscillator frequency can be above or below the frequency of the desired signal to produce a sum and a difference frequency, one of which is the frequency of interest. There are many types of mixers including unbalanced, single and double balanced mixers. Mixers may be further categorized as passive or active.
Conventional mixers are implemented in various semiconductor technologies such as silicon and gallium arsenide with diodes, bipolar junction transistors (BJT), field effect transistors (FET), or other variations of these types. Increasingly, integrated circuits (ICs) having complementary metal-oxide semiconductor (CMOS) technology are being used in RF circuits, including RF circuits for wireless (LAN) networks.
Thus, increasingly, direct conversion transceivers implemented with CMOS technology are being used in such wireless communication applications. Mixers used in direct conversion transceivers generally require low flicker (1/f) noise. The 1/f noise is an intrinsic noise phenomenon found in semiconductor devices. Active mixer circuits implemented in CMOS generally suffer from 1/f problems. Passive mixer circuits implemented in CMOS, on the other hand, generally exhibit a low noise figure. Thus, it is advantageous to use passive mixer circuits in direct conversion transceivers implemented with CMOS technology due to the improved noise figure.
A conventional CMOS implemented passive mixer circuit used in a receiver is shown in FIG. 1. In FIG. 1, the RF input signal to be down converted is fed into input terminals 101 and 103 and through capacitors 112 and 114 to the source terminals of the NMOS FET differential pairs 102 (M1), 104 (M2) and 106 (M3), 108 (M4) of passive mixer circuit 100. The local oscillator signal (LO) to be mixed with the RF signal is fed into input terminal 105 and through capacitor 116 to the gate terminals of FETs 102 and 108. The 180-degree phase shifted or “complementary” local oscillator signal (LOC) to be mixed with the RF signal is fed into input terminal 107 and through capacitor 118 to the gate terminals of FETs 104 and 106. A transformer or other phase shifting device (not shown) can provide this phase shift input.
A baseband (BB) signal is output at output terminals 113 and 115. DC power and biasing are provided via VBIAS terminal 109 through resistors 120 and 122 to the drain terminals of differential pairs 102, 104 and 106, 108 of passive mixer circuit 100. Capacitors 128 and 130 short higher frequencies appearing on output terminals 113 and 115 to VBIAS terminal 109. DC power and biasing are also provided via VLO BIAS terminal 111 through resistors 124 and 126 to the gate terminals of differential pairs 102, 104 and 106, 108.
Because the differential pairs 102, 104 and 106, 108 are driven by local oscillator signals that are 180 degrees out of phase, only one of FET pair 102, 108 or FET pair 104, 106 is on at a given time. Passive mixer circuit 100 multiplies the incoming signal RF-in with the local oscillator signal, producing sum and difference frequencies.
High linearity performance is required in mixer circuits used in wireless communication applications. Passive mixer circuits such as the one shown in FIG. 1 generally have poor linearity performance. One parameter by which the linearity performance of a mixer may be defined is the even order distortion of the mixer. The most significant form of even order distortion in a mixer is second order intermodulation (IM2) distortion. IM2 occurs when two interfering signals mix with each other through a second order nonlinearity to produce an intermodulation product at the sum and difference frequencies of the two interferers. IM2 may be produced, for example, by device mismatches, parametric imbalance, imperfect layout, and other device characteristic inequalities that cause imbalances in a differential pair.
A particular cause of IM2 in a passive mixer circuit like that shown in FIG. 1 are DC offsets caused by LO leakage. There are several mechanisms through which LO leakage may occur. For example, there may be conductive paths between components. This occurs because there is limited isolation from the LO input terminals of the mixer to the RF input terminals of the mixer. There may also be limited reverse isolation through the low-noise amplifying stages preceding the mixer. A parasitic signal path for signals through the substrate, as well as a lateral signal path through the substrate, can also occur. In addition to the conductive paths, there may also be radiated paths via the bond wires used to interconnect the circuit blocks to the outside world. The bond wires act as antennas and couple RF energy, such as that of the LO, to adjacent pins. The lack of LO isolation causes self mixing in the direct down converter that manifests as a DC offset at the baseband terminals of the mixer. This DC offset then negatively affects the bias voltages of the passive mixer 100.
Referring again to FIG. 1, differential pair 102, 104 will be used to describe a typical biasing method for the passive mixer 100. Differential pair 106, 108 is biased in a similar manner. A DC bias voltage of 1.2 Volts (V) is provided at VLO BIAS terminal 111. Thus, the DC voltage present at the gate terminals of NMOS FETs 102 or 104, respectively, is 1.2 V. A typical value of DC bias voltage provided at VBIAS terminal 109 is 0.6 V. Because mixer 100 is a passive mixer, there is no current flow through NMOS FETs 102 or 104. Because there is no current flow through NMOS FETs 102 or 104, the DC voltage present at output terminals 113 and 115, and also at the respective drain terminals of NMOS FETs 102 or 104, should ideally be 0.6 V, i.e. the DC voltage present at VBIAS terminal 109.
As stated above, because in operation FETs 102 and 104 are driven by local oscillator signals that are 180 degrees out of phase, only one of them is on at a given time. When either of the FETs 102 and 104 are turned on by the LO or LOC signals, respectively, the DC voltage present at their source terminals will be that present at their respective drain terminals, that is, ideally 0.6 V.
However, because of the DC offset manifested at the output terminals 113 and 115 by the LO self-mixing, the actual DC voltage present on output terminal 113 may vary from the DC voltage present on output 115. As an example, instead of the ideal DC voltage of 0.6 V that should be present at both output terminals 113 and 115, a DC voltage of 0.7 V may be present at output terminal 113, while a DC voltage of 0.5 V may be present at output terminal 115. Thus, in the present example there is a DC offset between output terminals 113 and 115 of 0.2 V. Therefore, when FET 102 is turned on, the DC voltage at its source terminal will be pulled up to 0.7 VDC. When FET 104 is turned on, the DC voltage at its source terminal will be pulled down to 0.5 VDC.
Referring now to FIGS. 2A through 2D, the negative effects on the linear performance of passive mixer 100 of LO self-mixing and the resulting DC offsets are illustrated. FIGS. 2A through 2D show waveforms present at the terminals of FETs 102 and 104 during operation of the passive mixer 100.
FIG. 2A represents the LO and LOC signals superimposed on one another on a horizontal axis representing time t. During operation of passive mixer 100, the LO and LOC signals are input to the gate terminals of FETs 102 and 104, respectively, as shown in FIG. 1. The LO and LOC signals switch their respective FETs on and off. As discussed above, the LO and LOC signals are 180 degrees out of phase and thus when FET 102 is switched on, FET 104 is switched off, and vice versa.
FIG. 2B represents output signals seen at the drain terminals of FETs 102 and 104. The slow-varying solid lines represent the baseband signal waveforms present at the terminals of FETs 102 and 104 during operation of the passive mixer 100. FIG. 2B shows that due to the DC offset of 0.2 V introduced by the LO self-mixing, the DC voltages at the drain terminals of FETs 102 and 104 deviate from each other by 0.2 V. Thus, the output signals present on the drain terminals of FETs 102 and 104 ride on DC levels that are offset by 0.2 V.
FIG. 2C represents the signal input seen at the source terminals of FETs 102 and 104. When either FET 102 or FET 104 turns on, the DC voltage at its drain terminal will be extended to its source terminal. Thus, as shown in FIG. 2C, when FET 102 turns on, the RF input signal at its source terminal will ride on a DC level that is shifted up from the original DC level of 0.6 V to 0.7 V. Similarly, when FET 104 turns on, the RF signal input at its source terminal will ride on a DC level that is shifted down from the original DC level of 0.6 V to 0.5 V.
FIG. 2D shows the gate-to-source voltage (Vgs) of FETs 102 and 104. As shown in FIG. 2D, the gate-to-source voltage of FET 102 (Vgs1) is not symmetrical to the gate-to-source voltage of FET 104 (Vgs2). This asymmetry results from the different DC voltages present on the source terminals of FETs 102 and 104 when they are turned on. When FET 102 is turned on, 0.7 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET 102 is determined by subtracting the DC voltage at its source terminal from the DC voltage at its gate terminal. The DC voltage from gate to source of FET 102 is 1.2 V−0.7 V=0.5 V. Thus, the DC level of signal Vgs1 will be shifted down from 0.6 V to 0.5 V. This results in reduced turn-on time for FET 102, as shown in FIG. 2D.
Similarly, when FET 104 is turned on, 0.5 V is present on its source terminal. The DC voltage from gate terminal to source terminal of FET 104 may be determined in the same manner as above to be 1.2 V−0.5 V=0.7 V. Thus, the DC level of signal Vgs2 will be shifted up from 0.6 V to 0.7 V This results in increased turn-on time for FET 104, as shown in FIG. 2D. The imbalance between Vgs1 and Vgs2 of passive mixer 100 shown in FIG. 2D results in increased IM2 distortion. Thus, the linearity performance of passive mixer 100 is degraded by the DC offset.
Efforts have been made to reduce LO self-mixing in order to reduce IM2 distortion. For example, attempts have been made to provide better isolation between the LO input terminals and RF input terminals of the mixer. However, these efforts have not been completely successful because parasitic and lateral signal paths through the substrate, as well as conductive paths between components, are difficult to overcome.
Thus, there remains a need for a passive mixer circuit for use in a direct conversion transceiver employed in wireless communication applications which IM2 distortion due to LO leakage induced DC offsets.